1. Field of the Invention
The present invention relates to a semiconductor device of a silicon on insulator (SOI) structure.
2. Description of the Related Background Art
In recent years, attention has been paid to a semiconductor device having a silicon on insulator (SOI) structure as a semiconductor device of low power consumption and high performance. FIG. 1 is a sectional view illustrating a general SOI device 500. As shown in FIG. 1, an SOI layer 530 composed of silicon is formed on a buried oxide film 520 (BOX; hereinafter, referred to as a BOX layer 520) formed on a silicon support substrate 510. The SOI layer 530 is separated from another SOI layer by an element separation oxide film formed at the surface of the BOX layer 520 using a local oxidation of silicon (LOCOS) method. In FIG. 1, the BOX layer 520 and the element separation oxide film are shown as one body. A gate electrode 540 is formed on the SOI layer 530. A side wall 550 is formed at each side of the gate electrode 540. A source (not shown) and a drain (not shown) are formed in the SOI layer 530. The source and drain constitute a field effect transistor, such as a complementary metal oxide semiconductor (CMOS), together with the gate electrode 540.
Since the BOX layer 520 is located below the SOI layer 530 in the SOI device as described above, parasitic capacitance of the source and the drain'becomes small, thereby achieving low power consumption and high performance. In addition, since the SOI layers are separated from each other, a latch up phenomenon does not occur, thereby achieving high precision layout. For these reasons, the SOI device is advantageous as compared with a conventional bulk silicon CMOS device disclosed in, for example, Japanese Patent Application Publication No. 2003-86708.
However, it has been confirmed that, in the SOI device, large stress is generated in the vicinities of the ends of the SOI layer 530, i.e., in the vicinities of the interfaces between the SOI layer 530 and the BOX layer 520, and the stress affects properties of the device. Specifically, since the SOI layer 530 is surrounded by the BOX layer 520 as shown in FIG. 1, stress ST is generated at the both ends of SOI layer 530 in directions indicated by arrows, with the result that the properties of the device are affected.
When large compressive stress, generated in the vicinities of the ends of the SOI layer, is applied to a channel region formed at the SOI layer, the following effects are generated. That is, carrier mobility is decreased, and on current is decreased, in an N type MOS transistor (hereinafter, simply referred to as an N type transistor). On the other hand, carrier mobility is increased, and on current is increased, in a P type MOS transistor (hereinafter, simply referred to as a P type transistor).
In the semiconductor device of the SOI structure, therefore, stress generated at the ends of the SOI layer is applied to the channel region, resulting in the occurrence of bias in transistor properties between the N type transistor and the P type transistor.